`timescale 1ns / 1ps
`include "def.v"

module M_DM(
    input clk,
    input reset,

    input [31:0] Addr,
    input [31:0] WD,
    input DMWrEn,
    
    output [31:0] RD
    );

    reg[31:0] mem[0:3071];
    integer i;

    initial begin
        for(i=0; i<3072; i=i+1) mem[i] = 32'd0;
    end

    always @(posedge clk) begin
        if(reset) begin
            for(i=0; i<3072; i=i+1) mem[i] = 32'd0;
        end 
        else if(DMWrEn) begin
            mem[Addr >> 2][31:0] <= WD;
        end
    end

    assign RD = mem[Addr >> 2][31:0];

endmodule
